Today, in conventional SRAM devices, 6-transistor CMOS SRAM cells are configured using planar MOS field effect transistors.
However, miniaturization of the device dimensions, which is performed with the aim of performance improvement such as integration density and operation speed, increases variation in the characteristics of the device. The variation obviously affects the operation stability of the SRAM. That is, the performances of the respective devices deviate randomly from the design target, so that mismatch occurs and bistability, which is indispensable for memory retention, is degraded. The variation in the device characteristics may eventually lead to malfunction, so that the yield will be lowered in the production process and reliability of the information systems will be lowered.
As an index for evaluating bistability, noise margin can be employed. The noise margin is defined as the maximum voltage of the noise amplitude which is allowed to be superposed on memory nodes. The noise margin for a read operation, a read margin, is the most difficult to ensure sufficiently among read, write and hold operations. The above-mentioned mismatch between the devices reduces the read margin. Therefore, when the SRAM device is designed, the noise margin is designed in advance so as to be large, so that it is possible to have a large margin even when there are variations in the device's characteristics in the production process.
The read margin cannot be increased without limit by device design, but it is inextricably linked with another index called a write margin. The write margin is defined as the maximum voltage amplitude which is allowed to be superposed on memory nodes when a write operation is performed, or the maximum voltage amplitude which is allowed to be superposed on word lines. When a circuit is designed such that the read margin increases, the write margin decreases.
In a conventional 6-transistor SRAM device, there are a few methods to enhance both the read and write margins. This was because the transistor's characteristics are fixed and it was difficult to change the transistor's characteristics according to the read or write operations.
For example, in Patent Document 1, there is disclosed an SRAM cell which uses double gate field effect transistors. The variation can be reduced to more than that of the known planar CMOS. Still, there was a problem with the performance variation of the double gate field effect transistors, and no method has been provided which increases both the read margin and the write margin.
In addition, in Patent Document 2, there is disclosed an SRAM device which uses four-terminal double gate field effect transistors of which two gates of the double gate field effect transistor are separated from each other. However, the SRAM device is configured to reduce the leakage current. This circuit is too complicated as a circuit for increasing both the read and the write margins at the same time. In addition, in Patent Document 2, there is no disclosure of the operation method or the peripheral devices for increasing both the read and the write margins.
Patent Document 1: Specification of US Patent Application Laid-Open Publication No. 2006-068531
Patent Document 2: JP-A-2005-260607